As a size and a design rule of a semiconductor device are reduced, an integration of a semiconductor device is increased. As an integration of a semiconductor device is increased, increasing an operational speed of a semiconductor device becomes important. A typical method of increasing an operational speed of a semiconductor device can be to reduce parasitic capacitance which may exist in the semiconductor device. A parasitic capacitance may be generated in various portions of a semiconductor device. For example, a parasitic capacitance can be generated in a dielectric layer disposed between a gate electrode and a channel region of source/drain region, which may reduce the operational speed of the associated device.